A. Vc1 > vc2 > vc3 when ig1 > ig2 > ig3. B. vc1 > vc2 > vc3 when ig1 < ig2 < ig3. C. Vc1 = vc2 = vc3 any value of ig. D. Vc1 > vc2 > vc3 when ig1 ã¢â€°â¥ ig2 &atil
A. < latching current but greater than holding current and gate signal is 0. B. less than holding current. C. < latching current but greater than holding current and gate signal is present. D. both (a) and (b).